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Vol: 52(66) No: 1 / March 2007 Hardware Architectures for Communication Protocols with Reference to MPLS Raymond Peterkin School of Information Technology and Engineering (SITE), University of Ottawa, Faculty of Engineering, 161 Louis Pasteur Ave., P.O. Box 450, Stn. A, K1N 6N5, Ottawa, Ontario, Canada, phone: (613) 562-5800,ext., e-mail: peterkin@site.uottawa.ca, web: http://www.site.uottawa.ca/~peterkin Dan Ionescu School of Information Technology and Engineering (SITE), University of Ottawa, Faculty of Engineering, 161 Louis Pasteur Ave., P.O. Box 450, Stn. A, K1N 6N5, Ottawa, Ontario, Canada, e-mail: ionescu@site.uottawa.ca, web: http://www.site.uottawa.ca/~ionescu Keywords: MPLS, protocol, hardware, FPGA. Abstract This paper presents an overview for hardware implementations of protocols used in Multi Protocol Label Switching (MPLS). MPLS is the protocol framework on which the attention of a network service provider is focused as it provides privacy and unbreakable security to users. It is meant to prioritize internet traffic and improve bandwidth utilization. As such it provides the possibility of associating Quality of Service (QoS) per flow. Furthermore MPLS increases the performance and efficiency of Internet applications. MPLS protocols are typically implemented by equipment providers in software. However, software based solutions decrease overall performance of MPLS and applications using MPLS. Therefore, hardware solutions are presented to illustrate the mechanisms through which improved performance is possible. An FPGA based architecture for MPLS is also presented to show how a combination of protocols and concepts may be used to effectively implement MPLS in hardware. References [1] Altera Corporation, Application Note 132: Implementing Multiprotocol Switching with Altera PLDs, version 1.0, January 2001. [2] E. Rosen, A. Viswanathan, R. Callon “RFC 3031: Multiprotocol Label Switching Architecture”, January 2001. [3] D. Awduche, L. Berger, D. Gan, T. Li, V. Srinivasan, G. Swallow, “RFC 3209: RSVP-TE: Extensions to RSVP for LSP Tunnels”, December 2001. [4] M. Abou-Gabal, R. Peterkin, D. Ionescu: “IS-IS protocol Hardware Architecture for VPN solutions”, in Proceedings of the 7th WSEAS Intern.Conf. on Communications, Athens, Greece, July 12-15, 2004. [5] D. Oran, “RFC 1142: OSI IS-IS Intra-domain Routing Protocol”, February 1990. [6] M. Abou-Gabal, R. Peterkin, D. Ionescu “An Architecture for a Hardware Implementation of the OSPF Protocol”, CAINE 2004. [7] J. Moy, “RFC 2328: OSPF Version 2”, April 1998. [8] M. Abou-Gabal, R. Peterkin, D. Ionescu, C. Lambiri, V. Groza, “A Shortest Path Processor for Traffic Engineering of VPN Services”,6th International Conference on Technical Informatics, IEEE, 2004. [9] H. Wang, M. Veeraraghavan, R. Karri, “A Hardware Implementation of a Signaling Protocol”, Opticomm 2002, July 2002. [10] J. Ash, Y. Lee, P. Ashwood-Smith, B. Jamoussi, D. Fedyk, D. Skalecki, L. Li, “RFC 3214: LSP Modification Using CR-LDP”, January 2002. [11] D. Gluskin and I. Cidon, “A Hardware Signaling Paradigm for Fine-Grained Resource Reservation”, Technion, CCIT Publication-433, June 2003, based on D. Gluskin “Hardware Oriented Resource reservation scheme for integrated networks”, Technion EE Master Thesis, March 2001. [12] Altera Corporation, Avalon Interface Specification, April 2005. [13] S. K. Long, R. R. Pillai, J. Biswas, T. C. Khong, “Call Performance Studies on the ATM Forum UNI Signalling”, http://www.krdl.org.sg/Research/Publications/ Papers/pillai_uni_perf.pdf. |