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Vol: 47(61) No: 2 / June 2002 The CREC Reconfigurable Computer: Preliminary Findings Octavian Cret Technical University of Cluj-Napoca, Computer Science Department, ROMANIA, , e-mail: Octavian.Cret@cs.utcluj.ro Kalman Pusztai Technical University of Cluj-Napoca, Computer Science Department, ROMANIA, , e-mail: Kalman.Pusztai@cs.utcluj.ro Cristian Vancea Technical University of Cluj-Napoca, Computer Science Department, ROMANIA, , e-mail: vcc@email.ro Balint Szente Technical University of Cluj-Napoca, Computer Science Department, ROMANIA, , e-mail: szente@rdslink.ro Keywords: Reconfigurable computing, Instruction Level Parallelism, VHDL, FPGA, RISC. Abstract The world of Reconfigurable Computing has known a significant development in the past years. The main research done in this field was oriented towards applications involving low granularity operations and high intrinsic parallelism. CREC is an original general-purpose Reconfigurable Computer whose architecture is generated through a Hardware / Software CoDesign process. The main idea of the CREC computer is to generate the best-suited hardware architecture for the execution of each software application. The CREC Parallel Compiler parses the source code and generates the hardware architecture, based on multiple Execution Units. The hardware architecture is described in VHDL code. The VHDL source code is generated by a program written in C. Finally, CREC is implemented in an FPGA device. The great flexibility offered by the general-purpose CREC system makes it interesting for a wide class of applications that mainly involve high intrinsic parallelism, but also other kinds of computations. References [1] DeHon, A. “Reconfigurable Architectures for General-Purpose Computing”. PhD. Thesis. Massachussets Institute of Technology (1996). [2] Singh, H. Lee, M.-H., Lu, G. Kurdahi, F. Baghrzadeh, N., Chaves Filho, E. “MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications”. IEEE Transactions on Computers, Vol. 49, no. 5, (May 2000). [3] Hauser, J., Wawrzynek, J. “Garp: A MIPS Processor with a Reconfigurable Coprocessor”. Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM \'97), April 16-18 (1997) |