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Vol: 4(4) No: 1 / March 1994 A Simulation Model for the Operation and Maintenance Functionality in ATM Switches Alexa Doboli Computer Science and Engineering Departament, Tehnical University of Timisoara, V. Parvan nr. 2, Timisoara, Romania Jonas Hallberg Departament of Computer and Information Science, Linkoping University, S-581 83 Linkoping, Sweden Petru Eles Computer Science and engineering Departament, Tehnical University of Timisoara, V. Parvan nr. 2, Timisoara, Romania Keywords: VHDL, ATM switches Abstract The paper presents a VHDL simulation model for the F4/F5 block of the ATM protocol, covering the block functionality as specified by standard references. The model consists of several processes, each implementing a relatively independent part of the block functionality. The model handles multiple virtual channel connections passing through the block. The management of ATM cells depends on the current “status” of the virtual path or virtual cannels and thus local tables are used for recording the global state of the block. For testing purposes we implemented a test bench providing the working environment of the F4/F5 block module and allowing automatic verification of the block functionality. By developing this VHDL model we produced a readable and at the same time executable specification of the F4/F5 functionality, according to the complex standard references. Thus we showed that VHDL can serve as a specification language for complex standard references. Thus we showed that VHDL can serve as a specification language for complex systems, regardless if they are intended to be implemented in hardware, software or both. References [1] de Frycker M., Asinchronous Transfer Mode, Ellis Horwood 1991. [2] Bellcore, Generic Requirements for Operations of Broadband Switching Systems,TANT/T-001248 issue 2, October 1993. [3] Larsson M. Ljungberg M., Rooth J., The ATM Switch Concept and the ATM pipe Switch, Ericsson Review, No. 1, 1993. [4] Rooholamini R., Chercassy V., Garver M., Finding the right ATM Switch for the Market, Computer, April 1994. [5] Staxen P., Vestin C., The Telecom Evolution in the Broudbund Era, Ericsson Review, 1993. [6] Svensson b., A. Testbench for the F4/F5 block of the ATM protocol, Master Thesis, Royal Tehnical University Stockholm, 1994. [7] Synthesia, The SINTIMINT VHDL Design System, Doc.No: SYNTHESIA 93 011 A, 1993. |