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Vol: 56(70) No: 3 / September 2011 An Approach for Generating Synthesizable VHDL Code from Data Flow Graphs Philip I. Necsulescu School of Information Technology and Engineering (SITE), University of Ottawa, Faculty of Graduate and Post Doctoral Studies, Ottawa, Canada, e-mail: necsup@gmail.com Voicu Groza School of Information Technology and Engineering (SITE), University of Ottawa, Faculty of Engineering, Ottawa, Canada, e-mail: groza@site.uottawa.ca Keywords: FPGA, Custom Instruction, Automatic Generation of VHDL code, Hardware Development, Data Flow Graph, Instruction Set Extension Abstract The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. In this article, the methodology used by SHIRA for the module used to generate syntheizable VHDL code from a Data Flow Graph (DFG) when it is used as the Intermediate Representation (IR) is described. The implementation of this approach is writen in Java, making use of Object Oriented Programming (OOP) principles. The SHIRA hardware generation module uses the DFG generated by the SHIRA toolchiain which itself is derived from a standard C program. The methodolgy is described for two cases: employing a separate component for each node in the DFG and when employing component reuses, that is allowing components to be used by multiple graph nodes. The two cases are then tested with some simple C programs on a standard Altera FPGA using a NIOS II/e processor with the generated VHDL code being added to the NIOS II/e instruction set as a Custom Instruction (CI). The results are then compared with the generic case of using only the standard processor instruction set, for the case when using a separate hardware component for each node in the DFG, and for the case allowing component reuse. References [1] Bertels, K, et al. “Hartes Toolchain Early Evaluation: Profiling, Compilation and HDL Generation,” in: Proceedings of International Conference on Field Programmable Logic and Applications (FPL 2007), 2007, pp. 402-408. [2] Rinker, R, et al., “An automated process for compiling dataflow graphs into reconfigurable hardware,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 130-139, Feb. 2001. [3] Yankova, Y, et al. “Automated HDL Generation: Comparative Evaluation,” in: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2007), 2007, pp. 2750-2753. [4] Shapiro, Daniel, “Design and Implementation of Instruction Set Extension Identification for a Multiprocessor System-on-chip Hardware/Software Co-design Toolchain,” M.A.Sc Thesis, University of Ottawa, Faculty of Engineering, Ottawa, ON, Canada, 2009. [5] Shapiro, D, et al. “Instruction Set Extension in the NIOS II: A Floating Point Divider for Complex Numbers,” in: Proceedings of 23rd Canadian Conference on Electrical and Computer Engineering (CCECE 2010), 2010, pp. 1-5. [6] Altera Corporation. “Quartus II Handbook Version 10.1 Volume 1: Design and Synthesis,” Dec. 2010. [7] A LTERA Cooperation, “Nios II Custom Instruction User Guide.” May 2008. http://www.altera.com/literature/ug/ug_nios2_custom_instruction.pdf. [8] Jerraya, A. A., et al. “Behavioral Synthesis and Component Resue with VHDL,” Norwell: Kluwer Academic Publishers, 1997. pp. 94-104. [9] Arato, P., Visegrady, T. and Jankovits, I., “High Level Synthesis of Pipelined Datapaths,” Budapest: John Wiley and Sons Limited. [10] Grosschadl, J et al. “Performance Evaluation of Instruction Set Extensions for Long Modular Arithmatic on a SPARC V8 Process,” in: Proceedings of 10th Euromicro Confernce on Digital System Design Architectures (DSD 2007), 2007, pp. 680-689. |